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OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC AMCC S3063 TRANSMITTER, S3064 RECEIVER, S3040 CDR, SUMITOMO SDM7128-XC FIBER OPTIC TRANSCEIVER AND AMCC/CIMARON AMAZON S4801 POS/ATM SONET MAPPER INTRODUCTION
The AMCC S3063 transmitter and S3064 receiver chips are fully integrated serialization/deserialization SONET STS-48/OC-48 (2.488 Gbps) interface devices. These devices are suitable for SONET based ATM applications, and can be used in conjunction with AMCC's S3040 Clock Recovery Unit (CRU). The AMCC S3063 and S3064 chips provide the first stage of the digital processing of a receive and a transmit SONET STS-48 bit-serial stream. In the receive path it converts a bit-serial data stream into a 16-bit parallel data format, and in the transmit path it converts 16-bit parallel data into bit-serial data. Figure 1 shows a typical application block diagram with an AMCC/ Cimaron AMAZON. Figure 2 shows more specifically the design details. Combining these devices provides a Physical Media Dependent (PMD) layer for SONET/SDH data transfer.
Figure 1. Typical Network Application Block Diagram
Sumitomo Fiber Optic Transceiver Module 1x9 SDM7128-XC
CRU AMCC S3040
AMCC S3064 Receiver
16
Parallel Input
AMCC S3063 Transmitter
AMCC/ Cimaron AMAZON STS-48C POS/ATM SONET MAPPER
Parallel Output
16
Signal Connect Description
Figure 1 shows the block diagram of this solution. 1. The Sumitomo fiber optic transceiver interfaces to the AMCC S3040 CRU chip via a bit-serial data stream. 2. After the clock is recovered from the bit-serial data stream the CRU chip transmits the recovered clock and re-timed data to the AMCC S3064 receiver. 3. The AMCC S3064 receiver transmits the bit-serial data converted into 16-bit parallel data to the AMCC/ Cimaron AMAZON. 4. The AMCC/Cimaron AMAZON transmits 16-bit parallel data to the AMCC S3063. 5. The AMCC S3063 transmits the bit-serial data to the Sumitomo fiber optic transceiver.
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OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC
Figure 2. S3063 Transmitter, S3064 Receiver, S3040 CDR, Sumitomo SDM7128-XC Fiber Optic Transceiver and AMCC/Cimaron AMAZON S4801 POS/ATM SONET Mapper Block Diagram
+5V Part +5V Part
1.0F 82 Zo = 50 0.1 F RD RDb 390 0.1 F 390 5V 510 SDN 510 SD CAP1 82 CAP2 "Logic 1" "Logic 0" 0.1 F KILLRXCLK FRAMEN POUT[15:0]P RSDP/N 100 0.1 F 0.1 F RSCLKP/N 100 0.1 F "Logic 1" "Logic 1" 3.3V 1 k 220 LSDP LSDN LSCLKP LSCLKN 0.1F LSCLKN POUT[15:0]N 16 220 16 220 POCLKP POCLKN RX_SONETCLK_P RX_SONETCLK_N RX_DATA[15:0]P RX_DATA[15:0]N
+3.3V Part
+3.3V Part
SERDATIP/N 100 SERDATOP/N
AMCC S3040
SERCLKOP/N REFCLKN REFCLKP LOCKDET
220 220
RX155MCKP/N RSTB DLEB SEARCH LLEB 470 AMCC S3064 OOF SDPECL LLCLKP LLCLKN LLDP LLDN LLDN
0.01 F 0.01 F Vcc 1k 6.2k Vcc 1k 6.2k Vcc 1k 6.2k Vcc 1k 6.2k 0.01 F 0.01 F
100 0.1F
LSCLKP
LLDP
AMCC/ Cimaron AMAZON S4801
Sumitomo Fiber Optic Transceiver Module 1x9 SDM7128-XC
150
LSDN
LLCLKN
LSDP 155MCKN 155MCKP 150 0.1 F 155.52 MHZ Oscillator LVPECL 100 0.1 F 180 "LOGIC 0" "LOGIC 1" "LOGIC 1" Zo = 50 LOCKDET TESTEN DLEB LLEB TSCLKP/N TSDP/N 0.1 F Zo = 50 CAP1
LLCLKP PICLKP PICLKN PCLKP 220 PCLKN 220 100
TX_SONETCLK_OUTP TX_SONETCLK_OUTN TX_SONETCLKP TX_SONETCLKN
AMCC S3063
REFCLKP/N
PIN[15:0]P 100 PIN[15:0]N PHINITP PHERRP PHINITN PHERRN 330 330
16 16
TX_DATA[15:0]P TX_DATA[15:0]N
TD 100 TDb
0.1 F
RSTB CAP2
RSTB
75 2.2F 75 RESET
2
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OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC
Parts List
The following is a parts list that is a recommendation to the designer to implement the circuit in Figures 1 and 2.
QTY 2 2 19 2 2 37 2 2 1 2 5 4 4 12 1 1 1 1 1 1 1 1 1 Part # or Equivalent Description Resistor, 75 , 10%, 1/8W, 805 or 603 package size Resistor, 82 , 10%, 1/8W, 805 or 603 package size Resistor, 100 , 10%, 1/8W, 805 or 603 package size Resistor, 150 , 10%, 1/8W, 805 or 603 package size Resistor, 180 , 10%, 1/8W, 805 or 603 package size Resistor, 220 , 10%, 1/8W, 805 or 603 package size Resistor, 330 , 10%, 1/8W, 805 or 603 package size Resistor, 390 , 10%, 1/8W, 805 or 603 package size Resistor, 470 , 10%, 1/8W, 805 or 603 package size Resistor, 510 , 10%, 1/8W, 805 or 603 package size Resistor, 1 k, 10%, 1/8W, 805 or 603 package size Resistor, 6.2 k, 10%, 1/8W, 805 or 603 package size Capacitor, 0.01 F, 10%, X7R, 16V, Surface Mount package Capacitor, 0.1 F, 10%, X7R, 16V, Surface Mount package Capacitor, 1.0 F, 10%, X7R, 16V, Surface Mount package Capacitor, 2.2 F, 10%, X7R, 16V, Surface Mount package SONET/SDH/ATM OC-48 Transmitter SONET/SDH/ATM OC-48 Receiver SONET/SDH Clock Recovery Unit AMCC/Cimaron OC-48 POS/ATM/SONET Mapper Sumitomo 5V Fiber Optic 1 x 9 Transceiver LVPECL Oscillator, +3.3V at 155.52 MHz NPN Transistor, 2N3904
S3063 S3064 S3040 S4801 AMAZON SDM7128-XC MMBT3904LTI
Theory Of Operation
1. The S3040 extracts the clock and re-times the data from the received differential PECL serial data input (SERDATIP/N) coming from the fiber optic receiver when the signal detect (SDN) is a PECL Low level. When signal detect (SDN) is at a PECL High level, the Phase Lock Loop (PLL) will be forced to lock to the PECL Reference Clock (REFCLKP/N). When the transmit PLL is locked to the reference clock input the lock detect (LOCKDET) TTL output goes High. 2. The S3064 receives the OC-48 (2.488 Gbit/s) scrambled NRZ data signals on the serial data stream (RSDP/N) LVPECL inputs. These inputs are clocked into the S3064 by the Receive Serial Clock (RSCLKP/N) LVPECL inputs. This clock is used by the receive section as the master clock to perform framing and deserialization functions. 3. When FRAMEN is disabled [FRAMEN = 0] and OOF is connected to ground, the Frame Pulse (FP) output is always inactive. The AMAZON device should be in default mode [RX_FRMR_INH = 0]. In this mode, the parallel input data is not assumed to be byte aligned. The AMAZON device will align to the incoming data. 4. The serial-bit data stream is then converted into a 16-bit parallel data format for output onto the dif-
ferential parallel output data bus (POUTP/ N[15:0]). The differential 16-bit parallel data is clocked out of the S3064 and into the AMCC/ Cimaron AMAZON S4801 with the differential Parallel Output Clock (POCLK). 5. The 16-bit parallel data is output from the AMCC/ Cimaron AMAZON S4801 into the S3063 differential parallel data input bus (PIN[15:0]) and is sampled by the Parallel Input Clock (PICLK) of the S3063. This clock is generated by the S3063 Parallel Clock (PCLK) which is fed into the AMCC/Cimaron AMAZON S4801 as the transmit clock (TX_SONETCLK) and then back into the PICLK input of the S3063. 6. The 16-bit parallel data is then converted to bitserial data and output through the Transmit Serial Data (TSDP/N) connections to the Sumitomo fiber optic transmitter (SDM7128-XC). 7. If the incoming serial-bit data stream is lost (when SDN is High) the lock detect circuit internal to the S3040 substitutes the external reference clock for the missing data stream clocking signal. This substitution of reference timing source is helpful to supply a continuous timing signal for the upstream devices and system operation even though valid received data does not exist. This switch over is a smooth transition with no noticeable phase shift.
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OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC
Terminations
The following is a list of terminations that need to be added for this particular design. 1. The 100 line to line termination resistor should be as close to the termination points as possible. 2. The 330 and 390 pull down resistors should be as close to the sources as possible. 3. The high frequency traces should be designed as 50 transmission lines with the termination as depicted in Figure 2. 4. All the termination resistors should be placed at the end of the transmission line, and the power supply decoupling should be placed as close as possible to the devices. 5. The PECL and LVPECL (differential pairs) traces should have equal length, (allows both signals to arrive at the destination at the same time) and be run in parallel and in close proximity of one another. This allows the same noise to couple onto both of the lines and become common mode noise which is ignored by differential inputs.
Conclusion
The Sumitomo fiber optic transceiver, AMCC's S3063/S3064/S3040 and the AMCC/Cimaron AMAZON S4801 solution combine to make a complete OC-48 Physical Media Dependent (PMD) layer for SONET/SDH data transfer.
Disclaimer
The circuit presented in this application note is based on data sheet information as well as standard implementation of termination schemes. It has not been built and tested in the lab environment.
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OC-48 APPLICATION NOTE WITH AMAZON/S3064/63/40 AND SUMITOMO FIBER OPTIC
Applied Micro Circuits Corporation * 6290 Sequence Dr., San Diego, CA 92121 Phone: (858) 450-9333 * (800) 755-2622 * Fax: (858) 450-9885 http://www.amcc.com
AMCC reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current. AMCC does not assume any liability arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the right to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered trademark of Applied Micro Circuits Corporation. Copyright (R) 1999 Applied Micro Circuits Corporation
September 27, 1999
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